1. Field of the Invention
The present invention relates to a phase comparator circuit, and more particularly to a multiplying-type phase comparator circuit having a large pull-in range.
2. Description of the Related Art
A conventional phase comparator circuit which is employed in a phase locked loop circuit (hereinafter referred to as "PLL circuit") and to which the present invention relates is shown in FIG. 1. The conventional phase comparator circuit shown in FIG. 1 is a quadrant multiplier circuit which comprises a constant-current source 11, a pair of collector resistors R1, R2 and a plurality of NPN bipolar transistors Q1, Q4, Q5, Q8-Q10. Each of the three pairs of transistors Q1, Q4; Q5, Q8; and Q9, Q10 constitutes an emitter-coupled differential circuit. Reference numerals 14 and 15 denote clock signal input terminals for receiving clock signals (CLK, CLK) from a voltage control oscillator (hereinafter referred to as "VCO"). Reference numerals 16 and 17 denote data input terminals for receiving data signals (DATA, DATA). A reference numeral 18 denotes an output terminal.
The function of the above circuit is explained hereunder with reference to FIG. 2 which shows a transfer characteristic thereof. Input signals V.sub.1 (t) are applied to the bases of the transistors Q9 and Q10, respectively, through the data input terminals 16, 17, whereby the distribution of bias currents to these two transistors Q9, Q10 is controlled. When high level outputs from the VCO are applied to the two cross-coupled transistor pairs Q1, Q4 and Q5, Q8, these transistor pairs function as two sets of single-pole double-throw switches which are driven in accordance with the input signals from the VCO.
Consequently, the relation between the DC output voltage "Vd" outputted at the output terminal 18 and the phase difference ".phi." is such that, as shown by a graph of transfer characteristics in FIG. 2, the output voltage Vd is at its minimum when .phi.=0, 2.pi., the same is 0 when .phi.=.pi./2, 3/2.pi., and the same is at its maximum when .phi.=.pi..
The conventional phase comparator circuit described above has the following defects. Since the circuit detects only a phase difference between the input signals V.sub.1 (t) and the outputs from the VCO, in the case where the frequency of the input signals V.sub.1 (t) and that of the VCO outputs are different from each other, the phase differences therebetween continues to circulate between 0 and 2.pi. and, thus, the output voltage Vd of the phase comparator circuit repeatedly changes between a positive output and a negative output, which leads to the possibility that no DC components may appear. For this reason, the PLL circuit employing such conventional phase comparator circuit 19 may face a problem in that, when the frequency of the input signals V.sub.1 (t) and that of the VCO outputs are different from each other, the control voltage for the VCO cannot be controlled by the output voltage of the phase comparator circuit, resulting in the failure of the desired synchronization. This is a problem to be solved by the invention, in the conventional phase comparator circuit.